ExaNIC FDK Extension Pack

ADVANCED FEATURES FOR LOW LATENCY SYSTEMS

The ExaNIC Firmware Development Kit Extension Pack (FDK-XP) adds ultra-low latency TCP connectivity along with improved PCS/MAC functionality to the existing ExaNIC FDK.

Low latency systems (such as tick-to-trade engines) require FPGA decision making logic to connect to TCP networking endpoints (e.g. trading venues). These connections depend on absolute minimum latency, but must fully support Ethernet, IP and TCP protocols.

The ExaNIC FDK Extension Pack (FDK-XP) simplifies and accelerates these tasks. It adds a new ultra-low latency PCS/MAC (for connecting FPGA logic to Ethernet networks) and an Accelerated TCP/IP Engine (ATE) (for connecting FPGA logic to TCP/IP endpoints).

The FDK-XP performance has been independently verified by the Securities Technology Analysis Center (STAC®). The STAC-T0 benchmark tests tick-to-trade performance using a simulated UDP/TCP exchange protocol. In the STAC report, the FDK-XP beat all previous records including reducing latency by well over 50% (with a minimum latency of 31ns) and operating at a maximum packet rate of over 11 million packets per second (limited by the benchmark suite).

Despite the impressive feature set, the FDK-XP has very lightweight resource requirements. Adding an FDK-XP ATE port typically incurs less than 1% additional resource utilization over the existing ExaNIC FDK.

The FDK-XP ships with two extra examples in addtion to the extensive example set in the ExaNIC FDK:

  • tcp_trigger_example is similar to native_trigger_example in the ExaNIC FDK. It sends a TCP packet from port 1 when it receives an Ethernet frame on port 0 and the first four bytes of the destination MAC address are all set (0xFF).

    This example is useful for testing the FDK-XP latency. Because of the very low latency, we recommend using high precision measurement such as the ExaNIC HPT or ExaLINK Fusion HPT for this type of measurement.

  • stac_t0implements the Stack Under Test side of the STAC-T0 benchmark as defined by Securities Technology Analysis Centre (STAC®). It receives simulated UDP market data through odd-numbered ports and sends out simulated TCP order responses from even-numbered ports when the STAC-T0 trigger condition is met.

    This firmware was the basis of the Securities Technology Analysis Center (STAC®) STAC-T0 benchmark results.

    GENERAL

    PERFORMANCE / RESOURCES

  • SERDES/PCS/MAC/CDC/TCP (TX+RX):
    • - Packet trigger,31-44ns response time. See full STAC report for detalis.
    • - Full loopback, 48ns (min)
  • Software latency (raw frame, ½RTT):
    • - 60 bytes - 790ns
    • - 300 bytes - 1060s
  • Resource Usage (for 1 ATE port):
    • - LUTs: 2030
    • - Flip Flops: 2237
    • - Block RAMs: 9
    • - Ultra RAMs: 1

    SUPPORT & WARRANTY

  • Purchase includes 1 year support and warranty, extended options available:

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