ExaNIC Firmware Development Kit

ULTRA-LOW LATENCY FPGA DEVELOPMENT KIT

The Exablaze FPGA firmware development kit (FDK) opens up the FPGA fabric inside the ExaNIC X10, X40, V5P, and V9P network cards to custom application development.

It allows customers to take advantage of Exablaze's ultra-low latency 10GbE, 1GbE MAC and PCIe DMA engine IP. By offloading latency critical parts of an application onto the FPGA, customers can eliminate the PCIe bus overhead and achieve true bump-in-the-wire latencies.

The FPGA development kit (FDK) is heavily optimized for low-latency applications such as high-frequency trading. Other use cases include deep packet inspection, advanced packet filtering and full line rate packet processing. The kit ships with the following examples:

  • trigger example shows how to pre-load the card with a reply ahead of time, and send it based on a simple mask/pattern match over received frames.
  • ping example demonstrates various functionality, including sending frames directly from the card, making use of hardware timestamping, and using custom frames to communicate with software.
  • steering example demonstrates how to perform user-defined flow steering. A simple destination IP based flow steering example is provided, which can easily be modified to perform steering based on application layer information.
  • bridging example demonstrates how to bridge two ports together, such that traffic received on one port is transmitted out of another.
  • soft responder example assists with one method of benchmarking the MAC latency of the ExaNIC. This example simply sends a response packet on receipt of the first byte off the wire.
  • native loopback example forwards received packets out a different port, including clock domain crossing from RX to TX and buffering.
  • chipscope example allows users to easily see relevant signals in chipscope, making performance measurement and debugging easy.
  • multi preload tx example allows the user to preload frames into the memory of the FPGA and then send them out several ports simultaneously in response to a single register write.
  • native register example which is a minimal example of how to use the PCI register interface.
  • native spam example which implements a simple packet generator.
  • extra BARs example which demonstrates how to use the additional register/memory spaces at BAR1/BAR4.
Building the example application is as simple as typing make, and the firmware image produced by the build process can be flashed to the card using our included firmware update software utility. In addition, a full bus functional model is included with the development kit for design simulation and verification

The development kit is fully integrated with our existing libexanic and ExaSOCK software libraries. These userspace direct access network drivers and a kernel bypass sockets library, allowing customers to progressively offload software functionality onto the FPGA.

An FDK Extension Pack is available for the ExaNIC V5P device. It offers an even lower latency PCS/MAC and Hardware Accelerated TCP Transmission. It is specifically designed for building ultra-low latency tick-to-trade systems.

Full documentation for the FDK can be found here.

    PERFORMANCE

    PROGRAMMING / DEBUGGING

  • Software based PCIe flash programming utility:
  • JTAG over PCIe port:
  • JTAG header on board:
  • Chipscope example included:

    SUPPORT & WARRANTY

  • Purchase includes 1 year support and warranty, extended options available:

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