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ExaNIC V5P

The ExaNIC V5P is an FPGA based network application card, specifically optimized for low-latency and high density datacenter applications. The device is built around a powerful Virtex Ultrascale Plus (VU5P) FPGA, packaged into a compact, half-height half-length, form factor and paired with 9GB of DDR4 DRAM and 28MB of QDR-IV SRAM.

Device installation

Installation of the ExaNIC V5P is similar to other ExaNIC devices. This page should be used be used in conjunction with the ExaNIC Installation section.

The V5P

Power

ExaNICs draw their power from the PCIe slot, which per the PCIe specification can be up to 25W for a low profile slot. The power consumption of an FPGA increases as the design complexity increases and more of the fabric is used. The V5P consumes less than 25W when the standard NIC image or example designs are used, however if customers fill the device up the product will use more than 25W.

For this reason, an additional 12V power connector & loom are supplied, which can be connected to a standard PCIe power connector found in your system.

Users can see if this external power is connected to the V5P by using exanic-config as shown below:

$ exanic-config exanic0
Device exanic0:
  Hardware type: ExaNIC V5P
  Temperature: 44.4 C   VCCint: 0.85 V   VCCaux: 1.81 V
  Fan speed: 5402 RPM
  Function: network interface
  Firmware date: 20180117 (Wed Jan 17 21:39:20 2018)
  External 12V power: detected
  PPS out: disabled

JTAG Access

The ExaNIC V5P has several methods for communicating with the FPGA via JTAG.

Xilinx Platform Cable

Users can plug the standard 14 pin JTAG cable from a Xilinx Platform Cable or equivalent JTAG pod into the V5P. Note that when this loom is inserted, connectivity from the USB JTAG circuitry to the FPGA is disabled.

USB JTAG

Users can plug a USB cable into a connector on the PCIe bracket of the V5P to gain JTAG access to the FPGA. Note that the USB JTAG interface and "14 way" interface cannot be used simultaneously. If a loom is connected between the 14 pin header and a Xilinx pod, the USB JTAG circuitry will be disconnected from the FPGA.

GPIO

A 10 pin connector is on the V5P for user GPIO. GND, 1V8 and 8 bits of GPIO are exposed. Please contact Exablaze for further details on this interface.

PPS

An MCX connector is onboard for PPS in/out time synchronization. Due to size & area restrictions, this connector could not be placed on the PCIe bracket. To use the connector, it is suggested that users run a small loom from the MCX connector to just outside the bracket for connection to a PPS network. Exablaze can supply the loom as well as PCIe brackets that have a small notch in them to allow the loom to pass through easily.

This page was last updated on Jan-24-2018.